The first thing I would recommend is using the Xilinx Foundation tools. Although it is buggy sometimes it will work for our "quick and dirty" project schematics. The advantage is the schematic capture tool similar to viewlogic that you can use. Read the following tutorials on how to use the tools.

If you would like to use jhdl, byu's own hardware descriptive language, you are free to do so. More recent documentation exists and people are currently downloading to the board with these projects. The downside is having to learn a complete new way of doing digital design and using several new tools. You would also have to modify your .cshrc file to get all of the different tools to work. If you would like to use these tools follow the following tutorials.

Use them and figure out how to download to the board. Before you start doing large designs I would suggest taking it easy at first. Make a small design and see if you can get it to download to the board.

JHDL tools:
    For this section I am going to basically refer you to the fpga laboratories tutorial pages as well as the 320 labs current tutorial pages. Follow the links to the jhdl site and look over the tutorials there. Other pages to note are lab1,lab3,lab5, and lab6 of the 320 web pages. By all means don't do the lab but look over the preliminary about how to set up your .cshrc files and how to use the jhdl tools. Lab 6 mentions how to use a clock. Clocks in jhdl are different from the other tools you will use. For some reason you have have a wire from the clock pin to pass through an ibuf and then the bufg. In lab 6 there is provided a bufg_hack that will let you simulate it properly.  Here is a snippet of code designed to implement a clock.

Wire clki = connect("clock",clock);
Wire clk_ibuf = wire(1,"clk_ibuf");
new ibuf(this,clki,clk_ibuf);
clki.addProperty(this,"LOC","P13");
Wire clk = wire(1,"clk");
new bufg_hack(this,clk_ibuf,clk);

clock is a wire passed in from the constructor that will be connected to the ibuf, it is renamed clki and then assigned a property of "LOC = P13". This addProperty method call is so that the fpga knows which pin to connect the wire to. This wire is then passed through the bufg_hack and out comes the clk wire. This is the wire that all clock signals will be connected to in your design.
 

this code will let you use the bufg_hack properly. Here is the code for the bufg_hack. It is designed to use one form of the bufg for simulation purposes but not for downloading or netlisting.

import byucc.jhdl.base.*;
import byucc.jhdl.Logic.*;
import byucc.jhdl.Xilinx.*;

public class bufg_hack extends Logic {

  public static CellInterface[] cell_interface = {
    in("i",1),
    out("o", 1),
  };

  public bufg_hack(Node parent,
              Wire i,
              Wire o) {

    super(parent);

    connect("i",i);
    connect("o",o);

    new byucc.jhdl.Xilinx.bufg_ann(this,i,o);
    new byucc.jhdl.Xilinx.buf(this,i,o).isNetlistable(false);

  }

}
This is the code written out for you to see.