A description of the course structure, the project, and the expectations for each team.

A description of the project specifications.

An overview of the software development strategy.

A summary of your Functional Specification. Part of your grade will be how well you came to meeting these specifications.

A summary of yourConcept Generation and Selection
Include a brief description of the different approaches you considered, a brief description of the criteria you applied to identify the best approach, and a detailed description of your selected approach.

Complete RF front-end design. At a minimum you should demonstrate filter specificaitons, analysis of adjacent channel interference, noise, and image rejection levels, knowledge of the external RF environment, hardware parts list, and a detailed block diagram, schematic, and chasis layout.

A working MATLAB demonstration. Demonstrate the operation on one of the provided data files. Provide a DSP loading estimate including count of the number of multiples and adds per second, estimate of the required level of optimization on the DSP processor (amount of parallelization). Identify (in code) data debug test points and what signals should look like (debug tools).

Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.

Direct the digital matched filter outputs to the D/A converters on the on the TI EVM.

Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.

The synchronizer loops do not need to be working. But include a fixed phase rotation in your DSP code as a place holder for the carrier phase synchronization PLL.

A detailed description of your schedule.

A cost estimate. (Show your calculations.)

A description of your progress to date relative to the milestones. (You should provide convincing evidence that your schedule will allow you to meet the deadlines for Milestones 2, 3, and 4.)

An update on your progress on the DSP code development.

An update on your progress on the RF hardware development.

A description of the changes that have been made in the design identified in the first design review.

Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.

Direct the interpolated matched filter outputs to the D/A converters on the on the TI EVM.

Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.

The AGC and symbol timing PLL should be working. It should be clear that the symbol timing PLL locks and that the AGC is working properly.

Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.

Direct the interpolated matched filter outputs to the D/A converters on the on the TI EVM.

Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.

The AGC and symbol timing PLL should be working. It should be clear that the symbol timing PLL locks and that the AGC is working properly.

All DSP functions, including symbol timing recovery should be functioning. Output the downsampled and interpolated matched filter outputs through the TI EVM D/A converters to the digital oscilloscope. What should we see?

Demonstrate a fully integrated system: Antenna, RF front-end, and baseband DSP subsystem.

Although not required for this milestone, you should make sure your system can communicate with the bit error rate tester.

All senior project competitions will be held in conjunction with Industry Day. The competition will be in the evening in the Garden Court in the Wilkenson Center (ELWC). Food (pizza) will be provided in Room 3224 ELWC.

Judges (external engineers from industry) will be on hand to evaluate your designs.

Your 2-page brochure is due at 12:00 noon that day.