1. C. Hilton, B. Nelson, A Circuit-Switched NOC for FPGA-Based Systems, Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL'2005), August 2005.
2. B. Catanzaro, B. Nelson, Higher Radix Floating-Point Representations for FPGA-Based Arithmetic, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'05), April 2005.
3. A. Poetter, J. Hunter, C. Patterson, P. Athanas, B. Nelson, and N. Steiner, JHDLBits: The Merging of Two Worlds, Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL'2004), August 2004.
4. J. Palmer, B. Nelson, A Parallel FFT Architecture for FPGAs, Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL'2004), August 2004, pages 948-953.
5. G. Ahlquist, B. Nelson, and M. Rice, Small and Fast Finite Field Multipliers for Field Programmable Gate Arrays (FPGAs), Proceedings of the 11th Annual NASA Symposium on VLSI Design, May 2003.
6. X. J. Wang and B. Nelson, Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs, In Kenneth L. Pocek and Jeffrey M. Arnold, editors, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '03), IEEE Computer Society, IEEE ComputerSociety Press, April 2003.
7. A. Slade and B. Nelson, Reconfigurable Computing Application Frameworks, In Kenneth L. Pocek and Jeffrey M. Arnold, editors, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '03), IEEE Computer Society, IEEE ComputerSociety Press, April 2003.
8. E. Roesler and B. Nelson. Debug Methods for Hybrid CPU/FPGA Systems. In Proceedings of The First IEEE International Conference on Field-Programmable Technology (FPT), pages 243­251, De-cember 2002.
9. E. Roesler and B. Nelson. Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture. In Proceedings of the 12th International Workshop on Field Programmable Logic andApplications (FPL'2002), pages 637­646, August 2002.
   Paper (c) Springer-Verlag, also available at http://www.springer.de/comp/lncs/index.html.
10. G. Ahlquist, B. Nelson, and M. Rice. Design and Synthesis of Small and Fast Finite Field Multipliers. In Proceedings of The 5th Annual Military and Aerospace Programmable Logic Device InternationalConference (MAPLD'2002), September 2002.  
11. B. Nelson. Configurable Computing and Sonar Processing - Architectures and Implementations. In ASILOMAR 2001, November 2001.  
12. B. Hutchings and B. Nelson. Giga Op DSP On FPGA. In Proceedings of ICASSP 2001, May 2001.  
13. T. Wheeler, P. Graham, B. Nelson, and B. Hutchings. Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. In Proceedings of the 11th Inter-national Workshop on Field Programmable Logic and Applications, volume 2147 of Lecture Notes inComputer Science, pages 483­492. Springer-Verlag, August/September 2001.  
14. B. Hutchings and B. Nelson. Unifying Simulation and Execution in a Design Environment for FPGA Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(1):201­205, February2001.  
15. Brad Hutchings, Brent Nelson, and Michael J. Wirthlin. Designing and Debugging Custom Computing Applications. IEEE Design & Test of Computers, 17(1):20­28, January 2000.  
16. B. Hutchings and B. Nelson. Using General-Purpose Programming Languages for FPGA Design. In Proceedings of the 37th Design Automation Conference, pages 561­566, June 2000.  
17. S. Scalera, M. Falco, and B. Nelson. A Reconfigurable Computing Architecture for Microsensors. In Kenneth L. Pocek and Jeffrey M. Arnold, editors, Proceedings of the IEEE Symposium on FPGAs forCustom Computing Machines (FCCM '00), pages 59­67. IEEE Computer Society, IEEE ComputerSociety Press, April 2000.  
18. P. Graham, B. Hutchings, and B. Nelson. Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'2000), April 2000.  
19. G. Ahlquist, B. Nelson, and M. Rice. Optimal Finite Field Multipliers for FPGAs. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL'1999), pages51­60, August 1999.  
20. B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD Suite for High-Performance FPGA Design. In K. L. Pocek and J. M. Arnold, editors, Proceedings of the IEEEWorkshop on FPGAs for Custom Computing Machines, pages 12­24, Napa, CA, April 1999. IEEEComputer Society, IEEE.  
21. P. Graham and B. Nelson. Reconfigurable Processors for High-Performance Embedded Digital Signal Processing. In Proceedings of the 9th International Workshop on Field Programmable Logic andApplications (FPL'1999), pages 1­10, August 1999.  
22. G. Ahlquist, M. Rice, and B. Nelson. Error Control Coding in Software Radios: An FPGA Approach. IEEE Personal COmmunications, 6(4):35­39, August 1999.  
23. Paul Graham and Brent Nelson. FPGA-Based Sonar Processing. In J. Cong and S. Kaptanoglu, editors, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 201­208,Monterey, CA, February 1998. ACM SIGDA, ACM Press.  
24. P. Graham and B. Nelson. Genetic Algorithms In Software and In Hardware -- A Performance Anal- ysis Of Workstation and Custom Computing Machine Implementations. In J. Arnold and K. Pocek,editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 216­225,Napa, CA, April 1996.  
25. K. Grimsrud, J. Archibald, R. Frost, and B. Nelson. Locality as a Visualization Tool. IEEE Transac- tions on Computers, pages 1319­1326, November 1996.  
26. G. Thompson, B. Nelson, and K. Flanagan. Transaction Processing Workloads - A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Analysis. In Proc. of Int. Workshopon Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS'96),pages 152­156, February 1996.  
27. K. Flanagan, B. Nelson, and G. Thompson. Incomplete Traces and Trace-Driven Simulation. In Proc. of Int. Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems(MASCOTS'96), pages 37­43, February 1996.  
28. P. Graham and B. Nelson. A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2. In W. Moore and W. Luk, editors, Field-Programmable Logic and Applications, pages352­361, Oxford, England, August 1995. Springer.  
29. A. Severson and B. Nelson. Throughput in a Counterflow Pipeline Processor. Computer Architecture News, April 1995.  
30. K. Grimsrud, J. Archibald, R. Frost, and B. Nelson. On the Accuracy of Memory Reference Models. In Proc. of 7th Int. Conf. On Modelling Techniques and Tools for Computer Performance Evaluation,pages 369­388. Springer Verlag, May 1994.  
31. B. Nelson, R. Jones, and D. Kirkpatrick. Simulation Event Pattern Checking with PROTO. In Proc. of the International Conference on Simulation and Hardware Description Languages, pages 115­121,January 1994.  
32. K. Grimsrud, J. Archibald, M. Ripley, K. Flanagan, and B. Nelson. BACH - A Hardware Monitor for Tracing Microprocessor-Based Systems. Microprocessors and Microsystems, 17(8):443­459, October1993.  
33. R. Smith, J. Archibald, and B. Nelson. Evaluating Performance of Prefetching Second Level Caches. Performance Evaluation Review - ACM Sigmetrics, 20(4):32­44, May 1993.  
34. K. Grimsrud, J. Archibald, and B. Nelson. Multiple Prefetch Adaptive Disk Caching. IEEE Transac- tions on Knowledge and Data Engineering, 5(1):88­103, February 1993.  
35. K. Flanagan, B. Nelson, J. Archibald, and K. Grimsrud. Incomplete Trace Data and Trace-Driven Sim- ulation. In Proc. of Int. Workshop on Modeling, Analysis, and Simulation of Computer and Telecom-munication Systems (MASCOTS'93), pages 203­209, January 1993.  
36. K. Grimsrud, J. Archibald, R. Frost, and B. Nelson. Estimation of Simulation Error Due to Trace Inaccuracies. In Proc. of 26th Asilomar Conference on Signals, Systems and Computers, October1992.  
37. K. Flanagan, B. Nelson andJ. Archibald, and K. Grimsrud. BACH: BYU Address Collection Hard- ware; The Collection of Complete Traces. In Proc. of 6th Int. Conf. on Modeling Techniques and Toolsfor Computer Performance Evaluation, pages 51­65, September 1992.  
38. L. Salmon, J. Archibald, and B. Nelson. Impact of Advanced Packaging Technologies on Computer Architecture. In IEEE Computer Society Workshop, February 1992.  
39. B. Nelson, J. Archibald, and K. Flanagan. Performance Analysis of Inclusion Effects in Multi-Level Multiprocessor Caches. In Proc. of the Third IEEE Symp. on Parallel and Distributed Processing,pages 513­516, December 1992.  
40. D. Boggs, J. Archibald, and B. Nelson. Accurate Performance Evaluation of Systems with Two- Level Caches using Trace-Driven Simulation. In Proc. of the Fourth ISMM Int. Conf. on Parallel andDistributed Computing and Systems, pages 240­244, October 1991.  
41. P. Michelsen, J. Archibald, and B. Nelson. Numerically Intensive Computing on the New Super- workstations: Supercomputing on the Cheap? In Proc. of 9th Annual Conf. on University Programsin Computer-Aided Engineering, Design and Manufacturing (UPCAEDM 91), pages 138­143, May1991.  
42. S. Son, B. Nelson, and J. Archibald. Efficient Utilization of Distributed Workstation Resources. In Proc. of 9th Annual Conf. on University Programs in Computer-Aided Engineering, Design and Man-ufacturing (UPCAEDM 91), pages 121­126, May 1991.  
43. T. Li, S. Zhao, and B. Nelson. Parallel Iterative Deepening for Optimization. In Proc. of Parallel and Distributed Computing of Systems, 1990.  
44. T. Li, B. Nelson, and K. Flanagan. CMOS Implementation of a Correlator for Delta-Modulated Signals. International Journal of Electronics, 67(2):215­220, August 1989.  
45. T. Li and B. Nelson. Designing Systolic Processors Using SYSIM2. Progress in Computer-Aided VLSI Design, 3, 1989.  
46. J. Lawlor, B. Nelson, and J. Archibald. CSIM: A Discrete Simulation Package for C. In Proceedings of the 1989 Summer Computer Simulation Conference, pages 20­24, July 1989.  
47. J. Flanagan, D.Morrell, R. Frost, C. Read, and B. Nelson. Vector Quantization Codebook Generation Using Simulated Annealing. In Proceedings of International Conference on Acoustics, Speech, andSignal Processing, May 1989.  
48. J. Flanagan and B. Nelson. Processor Design Using Path Programmable Logic. In Proceedings of 1988 IEEE International Conference on Computer Design: VLSI in Computers & Processors, October1988.  
49. T. Li, B. Nelson, K. Flanagan, and C. Read. A Multiprogrammed Parallel Architecture For Digital Signal Processing. In Proceedings of the 1987 IEEE International Conference on Acoustics, Speech,and Signal Processing, April 1987.  
50. B. Nelson, D. Morrell, C. Read, and K. Smith. The PPL Integrated Circuit Design Methodology. Computer-Aided Design, 18(9):481­488, November 1986.  
51. B. Nelson and C. Read. A Bit-Seral VLSI Vector Quantizer. In Proceedings of the 1986 IEEE-IECEJ- ASJ International Conference on Acoustics, Speech, and Signal Processing, April 1986.  
52. T. Li and B. Nelson. Parallel Processing of Linear Quadtrees. In Proceedings of the First International Conference on Future Advances in Computing, February 1986.  
53. L. Hollaarand B. Nelsonand T. Carter and R. Lorie. The Structure And Operation of a Relational Database System in a Cell-Oriented Integrated Circuit Design System. In Proceedings of the 21stDesign Automation Conference, pages 117­125, June 1984.  
54. E. Organick, T. Carter, M Maloney, A. Davis, A. Hayes, D.Klass, G. Lindstrom, B. Nelson, and K. Smith. Transforming An Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Envi-ronment: A First Experiment. IEEE Software, pages 31­49, January 1984.  
55. B. Nelson, K. Smith, and T. Carter. Cost Effective VLSI Design System. In IEEE International Symposium on Circuits and Systems, May 1983.  
56. K. Smith, B. Nelson, and K. Stevens. Student-Designed VLSI at the University of Utah. In Proceedings of the IEEE 2nd CAD/CAM Workshop, December 1983.  
57. K. Smith, B. Nelson, T. Carter, and A. Hayes. Computer-aided Design of Integrated Circuits Using Path-Programmable Logic. In IEEE Electro 83 Professional Program Session Record, April 1983.  
58. T. Carter, K. Smith, B. Nelson, A. Hayes, and D. Fisher. Path-Programmable Logic and the Use of Cadds2/VLSI. In Proceedings of the Fourth Annual International Computervision User Conference,pages 523­528, September 1982.