phase shift
bit sequence     (degrees)    
----------------------------
     00              0
     01            +90
     10            -90
     11            180

• Complete RF front-end design. At a minimum you should demonstrate
  • Filter specifications
  • Analysis of adjacent channel interference, noise, and image rejection levels
  • Knowledge of the external RF environment
  • Hardware parts list
  • Detailed block diagram, schematic, and chassis layout.
• A Working Matlab Code Demonstration
  • Demonstrate operation on provided data file.
  • DSP loading estimate including count of the number of multiples and adds per second, estimate of the required level of optimization on the DSP processor (amount of parallelization).
  • Identify (in code) data debug test points and what signals should look like (debug tools).

• RF Front-End Demonstration
  • Demonstrate working RF front-end without antenna, without link budget computation, and without integration with the DSP.
  • Must be built on the metal chassis.
• DSP Matched Filter Demonstration
  • Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.
  • Direct the digital matched filter outputs to the D/A converters on the on the TI EVM.
  • Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.
  • The synchronizer loops do not need to be working. But include a fixed phase rotation in your DSP code as a place holder for the carrier phase synchronization PLL.

• Connect the I-Q Baseband outputs of the ESG-D Signal Generator to the A/D converter inputs on the TI EVM.
• Direct the digital matched filter outputs to the D/A converters on the on the TI EVM.
• Connect the TI EVM D/A converter outputs to the digital oscilloscope for display.
• The AGC and carrier phase synchronization PLL should be working. Design a test to demonstrate that the carrier phase PLL locks and that the AGC is working properly.

• All DSP functions, including symbol timing recovery should be functioning. Output the downsampled and interpolated matched filter outputs through the TI EVM D/A converters to the digital oscilloscope. What should we see?
• Demonstrate a fully integrated system: Antenna, RF front-end, and baseband DSP subsystem.
• Although not required for this milestone, you should make sure your system can communicate with the bit error rate tester.

• All senior project competitions will be held in conjunction with Industry Day and the Alumni Reunion. The competition will be in the morning in the Clyde Lounge. We will probably go in between rounds of the robot-soccer competition.
• Final Oral presentations will be made to the judges (external engineers from industry). This will probably be in the afternoon. Exact time and location to be announced...